Icestorm: ST1 (multiple, 1 reg, 4S) measurements

Code:

  st1 { v0.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29667	1003	1	1002	1000	4000	1000	1000	2000	1	1000
61004	29246	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29245	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29239	1001	1	1000	1000	4000	1000	1000	2002	1	1000
61004	29471	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29914	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29215	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29255	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29237	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29294	1001	1	1000	1000	4000	1000	1000	2000	1	1000

Count: 8

Code:

  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]
  st1 { v0.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80149	80119	101	80018	100	80001	300	1359974	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80037	300	1360312	80137	200	80052	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80036	300	1360335	80136	200	80051	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	80101	200	80008	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80151	80029	11	80018	10	80001	30	1359850	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160104	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1359886	80011	20	80008	20	160016	1	80000	10

ST1 (multiple, 1 reg, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations