Icestorm: ST1 (multiple, 1 reg, 8H) measurements

Code:

  st1 { v0.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29374	1003	1	1002	1000	4000	1000	1000	2000	1	1000
61004	29588	1001	1	1000	1000	4000	1000	1000	2002	1	1000
61004	29294	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29134	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29124	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29104	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29107	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29124	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29113	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29115	1001	1	1000	1000	4000	1000	1000	2000	1	1000

Count: 8

Code:

  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]
  st1 { v0.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80533	80191	101	80090	100	80001	300	1359956	0	80101	200	80008	0	200	160016	1	80000	100
80204	80038	80101	101	80000	100	80001	300	1359868	0	80101	200	80008	0	200	160016	1	80000	100
80206	80107	80135	101	80034	100	80001	300	1360406	0	80101	200	80008	0	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80069	300	1360221	0	80169	200	80092	0	200	160104	1	80000	100
80204	80038	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80038	80101	101	80000	100	80001	300	1359868	0	80101	200	80008	0	200	160016	1	80000	100
80206	80122	80135	101	80034	100	80001	300	1360460	0	80101	200	80008	0	200	160016	1	80000	100
80204	80038	80101	101	80000	100	80001	300	1359868	0	80101	200	80008	0	200	160016	1	80000	100
80204	80038	80101	101	80000	100	80001	300	1359868	0	80101	200	80008	0	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	0	80101	200	80008	0	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80151	80029	11	80018	10	80034	30	1360449	80044	20	80049	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80035	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80025	80075	80028	11	80017	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	1	80000	10

ST1 (multiple, 1 reg, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations