Icestorm: ST1 (multiple, 2 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29745	2005	1	2004	2000	8000	2000	2000	4000	1	2000
62004	29398	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29394	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62005	29400	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29450	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29363	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29416	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29339	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29339	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29341	2001	1	2000	2000	8000	2000	2000	4000	1	2000

Count: 8

Code:

  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]
  st1 { v0.16b, v1.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	160153	160119	101	160018	100	160034	300	2720084	160134	200	160048	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320096	1	160000	100
160205	160078	160118	101	160017	100	160001	300	2720064	160101	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320096	1	160000	100
160204	160039	160101	101	160000	100	160002	300	2713797	160102	200	160008	200	320016	1	160000	100
160204	160039	160101	101	160000	100	160001	300	2719886	160101	200	160008	200	320016	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	160155	160029	11	160018	10	160001	30	2720010	160011	20	160008	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320096	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160034	30	2719960	160044	20	160048	20	320096	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10
160024	160037	160011	11	160000	10	160000	30	2719847	160010	20	160000	20	320000	1	160000	10

ST1 (multiple, 2 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations