Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 2 regs, 2S)

Test 1: uops

Code:

  st1 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
62006294972005110021002100210008751400020001000100020002000110001000
62004293042001110001000100010008751400020001000100020002000110001000
62004295792001110001000100010008751400020001000100020002000110001000
62004293562001110001000100010008751400020001000100020002000110001000
62004293512001110001000100010008751400020001000100020002000110001000
62004296542001110001000100010008751400020001000100020002000110001000
62004297042001110001000100010008751400020001000100020002000110001000
62004294132001110001000100010008751400020001000100020002000110001000
62004293502001110001000100010008751400020001000100020002000110001000
62004293372001110001000100010008751400020001000100020002000110001000

Test 2: throughput

Count: 8

Code:

  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  st1 { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680155160155101800368001810080038800013001360030320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100
16020480047160105101800048000010080006800013001360102320026160107200800068000620016001216001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002680153160065118003680018108003880001301360066320026160017208000680006201600121600121800008000010
16002480047160015118000480000108000680031301360515320146160077208003680036201600121600121800008000010
16002480047160015118000480000108000680001301360102320026160017208000680006201600121600121800008000010
16002480047160015118000480000108000680001301360102320026160017208000680006201600121600121800008000010
16002580106160059118003080018108003080001301360228320026160017208000680006201600121600121800008000010
16002580105160064118003580018108003780001301360102320026160017208000680006201600121600121800008000010
16002480047160015118000480000108000680000301360099320000160010208000080000201600741600741800008000010
16002480047160015118000480000108000680001301360102320026160017208000680006201600001600001800008000010
16002480047160015118000480000108000680032301360505320150160079208003780037201600121600121800008000010
16002580109160063118003480018108003680001301360138320026160017208000680006201600121600121800008000010