Icestorm: ST1 (multiple, 2 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29815	2005	1	2004	2000	8000	2000	2000	4000	1	2000
62004	29410	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29406	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29418	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29406	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29413	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29407	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29414	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29703	2001	1	2000	2000	8000	2000	2000	4000	1	2000
62004	29414	2001	1	2000	2000	8000	2000	2000	4000	1	2000

Count: 8

Code:

  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]
  st1 { v0.4s, v1.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	160153	160119	101	160018	100	160034	300	2720120	160134	200	160048	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160205	160073	160118	101	160017	100	160001	300	2720136	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160205	160073	160118	101	160017	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100
160204	160045	160101	101	160000	100	160001	300	2720010	160101	200	160008	200	320016	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	160147	160029	11	160018	10	160001	30	2720010	160011	20	160008	20	320096	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160067	30	2721384	160077	20	160088	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160039	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160025	160067	160028	11	160017	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10
160024	160043	160011	11	160000	10	160000	30	2719883	160010	20	160000	20	320000	1	160000	10

ST1 (multiple, 2 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations