Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.8h, v1.8h }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 62005 | 29731 | 2013 | 1 | 2012 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29420 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29411 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29386 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29448 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29307 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29306 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29305 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29304 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
| 62004 | 29306 | 2001 | 1 | 2000 | 2000 | 8000 | 2000 | 2000 | 4000 | 1 | 2000 |
Count: 8
Code:
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]
st1 { v0.8h, v1.8h }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 160205 | 160149 | 160119 | 101 | 160018 | 100 | 160001 | 300 | 2720010 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720010 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 201 | 320096 | 2 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320096 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
| 160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 1 | 160000 | 100 |
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 160025 | 160285 | 160029 | 11 | 160018 | 10 | 160000 | 30 | 2719971 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160034 | 30 | 2720120 | 160044 | 20 | 160048 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160052 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160025 | 160073 | 160028 | 11 | 160017 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160024 | 160045 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
| 160025 | 160087 | 160028 | 11 | 160017 | 10 | 160000 | 30 | 2720007 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |