Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.16b, v1.16b, v2.16b }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 63005 | 29588 | 3007 | 1 | 3006 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29697 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 30017 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29319 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29316 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29342 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29316 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29324 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29321 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
| 63004 | 29313 | 3001 | 1 | 3000 | 3000 | 12000 | 3000 | 3000 | 6000 | 1 | 3000 |
Count: 8
Code:
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 3.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240205 | 240150 | 240119 | 101 | 240018 | 100 | 240001 | 300 | 4079912 | 240101 | 200 | 240008 | 200 | 480104 | 1 | 240000 | 100 |
| 240204 | 240054 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240037 | 300 | 4080168 | 240137 | 200 | 240052 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240205 | 240075 | 240118 | 101 | 240017 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240035 | 300 | 4080159 | 240135 | 200 | 240048 | 200 | 480016 | 1 | 240000 | 100 |
| 240204 | 240047 | 240101 | 101 | 240000 | 100 | 240001 | 300 | 4080046 | 240101 | 200 | 240008 | 200 | 480016 | 1 | 240000 | 100 |
Result (median cycles for code divided by count): 3.0005
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240025 | 240150 | 240029 | 11 | 240018 | 10 | 240001 | 30 | 4079850 | 240011 | 20 | 240008 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240034 | 30 | 4079996 | 240044 | 20 | 240048 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480096 | 1 | 240000 | 10 |
| 240024 | 240046 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240035 | 30 | 4079999 | 240045 | 20 | 240048 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240047 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |
| 240024 | 240039 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 4079883 | 240010 | 20 | 240000 | 20 | 480000 | 1 | 240000 | 10 |