Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 3 regs, 2S)

Test 1: uops

Code:

  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
630062955730071100220041002200012750400030002000100040002000120001000
630042930130011100020001000200012750400030002000100040002000120001000
630042930230011100020001000200012750400030002000100040002000120001000
630042930130011100020001000200012750400030002000100040002000120001000
630042931030011100020001000200012750400030002000100040002000120001000
630042930130011100020001000200012750400030002000100040002000120001000
630042930330011100020001000200012750400030002000100040002000120001000
630042930130011100020001000200012750400030002000100040002000120001000
630042930130011100020001000200012750400030002000100040002000120001000
630042930830011100020001000200012750400030002000100040002000120001000

Test 2: throughput

Count: 8

Code:

  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402061601532401431018002416001810080025160001300271999732001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271986832001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160037300272073232009724016120016004880024200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100
2402051600832401431018002416001810080025160001300271990432001324010420016000880004200320016160008116000080000100
2402041600382401031018000216000010080003160001300271990432001324010420016000880004200320016160008116000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2400261601462400531180024160018108002516003830272076632009824007220160049800252032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030272018932000024001020160000800002032000016000011600008000010
2400251600832400501180021160018108002116000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032009616004811600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010
2400241600382400111180000160000108000016000030271990132000024001020160000800002032000016000011600008000010