Icestorm: ST1 (multiple, 3 regs, 4S) measurements

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29505	3007	1	3006	3000	12000	3000	3000	6000	1	3000
63004	29311	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29303	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29349	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29360	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29308	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29333	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29303	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29306	3001	1	3000	3000	12000	3000	3000	6000	1	3000
63004	29308	3001	1	3000	3000	12000	3000	3000	6000	1	3000

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]
  st1 { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240206	240191	240136	101	240035	100	240034	300	4081001	240134	200	240048	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240037	300	4080132	240137	200	240052	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240001	300	4080010	240101	200	240008	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240001	300	4080010	240101	200	240008	200	480096	1	240000	100
240204	240045	240101	101	240000	100	240001	300	4080010	240101	200	240008	200	480016	1	240000	100
240204	240053	240101	101	240000	100	240001	300	4080010	240101	200	240008	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240034	307	4080088	240136	202	240047	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240001	300	4080010	240101	200	240008	200	480016	1	240000	100
240204	240045	240101	101	240000	100	240001	300	4080136	240101	200	240008	200	480016	1	240000	100
240205	240082	240118	101	240017	100	240001	300	4080010	240101	200	240008	200	480016	1	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	240146	240029	11	240018	10	240001	30	4080010	240011	20	240008	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480000	1	240000	10
240025	240065	240028	11	240017	10	240000	30	4079811	240010	20	240000	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480096	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480000	1	240000	10
240025	240065	240028	11	240017	10	240000	30	4079973	240010	20	240000	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480000	1	240000	10
240024	240037	240011	11	240000	10	240000	30	4079847	240010	20	240000	20	480096	1	240000	10

ST1 (multiple, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations