Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.001
Load/store unit issues: 4.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 64005 | 29875 | 4009 | 1 | 4008 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29508 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29466 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29467 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29467 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29489 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29467 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8008 | 1 | 4000 |
| 64004 | 29469 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29468 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
| 64004 | 29465 | 4001 | 1 | 4000 | 4000 | 16000 | 4000 | 4000 | 8000 | 1 | 4000 |
Count: 8
Code:
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 4.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 320206 | 320201 | 320136 | 101 | 320035 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320205 | 320082 | 320118 | 101 | 320017 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640096 | 1 | 320000 | 100 |
| 320204 | 320054 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640096 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640016 | 1 | 320000 | 100 |
| 320204 | 320047 | 320101 | 101 | 320000 | 100 | 320003 | 300 | 5440053 | 320103 | 200 | 320008 | 200 | 640096 | 1 | 320000 | 100 |
Result (median cycles for code divided by count): 4.0005
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 320026 | 320314 | 320046 | 11 | 320035 | 10 | 320003 | 30 | 5440004 | 320013 | 20 | 320008 | 20 | 640000 | 1 | 320000 | 10 |
| 320024 | 320039 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320025 | 320090 | 320028 | 11 | 320017 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320024 | 320039 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 5440331 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320025 | 320067 | 320028 | 11 | 320017 | 10 | 320000 | 30 | 5439834 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320024 | 320039 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320025 | 320067 | 320028 | 11 | 320017 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640096 | 1 | 320000 | 10 |
| 320025 | 320082 | 320028 | 11 | 320017 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640096 | 1 | 320000 | 10 |
| 320024 | 320039 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640000 | 1 | 320000 | 10 |
| 320024 | 320039 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 5439883 | 320010 | 20 | 320000 | 20 | 640096 | 1 | 320000 | 10 |