Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 4 regs, 2S)

Test 1: uops

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640062977740091200420042004200017751800040002000200040004000120002000
640042947740011200020002000200017751800040002000200040004000120002000
640042946740011200020002000200017751800040002000200040004000120002000
640042947940011200020002000200017751800040002000200040004000120002000
640042966740011200020002000200017751800040002000200040004000120002000
640042948240011200020002000200017751800040002000200040004000120002000
640042972440011200020002000200017751800040002000200040004000120002000
640042978440011200020002000200017751800040002000200040004000120002000
640042948540011200020002000200017751800040002000200040004000120002000
640042948540011200020002000200017751800040002000200040004000120002000

Test 2: throughput

Count: 8

Code:

  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
32020716018932022310116008616003610016008816000230027200206400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200963200961160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200963200961160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200163200161160000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
32002616014632007511160046160018101600481600023027202366400263200182016000816000820320000320000116000016000010
32002416004932001111160000160000101600001600003027199556400003200102016000016000020320000320000116000016000010
32002516012032007311160044160018101600461600003027201356400003200102016000016000020320000320000116000016000010
32002416004932001111160000160000101600001600003027199556400003200102016000016000020320000320000116000016000010
32002416004932001111160000160000101600001600003027199556400003200102016000016000020320000320000116000016000010
32002416003932001111160000160000101600001600003027201356400003200102016000016000020320096320096116000016000010
32002416003932001111160000160000101600001600003027199556400003200102016000016000020320000320000116000016000010
32002416004932001111160000160000101600001600003027201356400003200102016000016000020320000320000116000016000010
32002416004932001111160000160000101600001600003027201356400003200102016000016000020320000320000116000016000010
32002416003932001111160000160000101600001600383027207536401863200942016004816004820320000320000116000016000010