Icestorm: ST1 (multiple, 4 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	29751	4019	1	4018	4000	16000	4000	4000	8000	1	4000
64004	29421	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29415	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29421	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29393	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29405	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29420	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29415	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29421	4001	1	4000	4000	16000	4000	4000	8000	1	4000
64004	29424	4001	1	4000	4000	16000	4000	4000	8000	1	4000

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320205	320146	320119	101	320018	100	320003	300	5439919	320103	200	320008	200	640016	1	320000	100
320204	320037	320101	101	320000	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320205	320074	320118	101	320017	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320204	320037	320101	101	320000	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320205	320086	320118	101	320017	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320204	320037	320101	101	320000	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320205	320074	320118	101	320017	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320204	320037	320101	101	320000	100	320003	300	5439983	320103	200	320008	200	640016	1	320000	100
320205	320065	320118	101	320017	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100
320204	320037	320101	101	320000	100	320003	300	5439857	320103	200	320008	200	640016	1	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320025	320148	320029	11	320018	10	320003	30	5439893	320013	20	320008	20	640000	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640096	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640000	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640096	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640000	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640096	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640000	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640096	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5439883	320010	20	320000	20	640000	1	320000	10
320024	320039	320011	11	320000	10	320000	30	5440135	320010	20	320000	20	640000	1	320000	10

ST1 (multiple, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations