Icestorm: ST1 (multiple, post-index, 1 reg, 16B) measurements

Code:

  st1 { v0.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29265	2005	1003	1002	1002	1000	3000	4000	2000	1000	3000	1001	1000
61004	29074	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29076	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29079	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29074	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29078	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29072	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000

Count: 8

Code:

  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8
  st1 { v0.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80149	160158	80140	80018	80143	80003	1023961	1360008	160109	200	80010	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80036	958939	1360349	160182	202	80046	200	240024	80004	80000	100
80204	80057	160104	80104	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80001	420946	1360086	160105	200	80008	200	240024	80002	80000	100
80204	80047	160102	80102	80000	80104	80037	1333640	1360241	160180	200	80051	200	240024	80002	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80151	160068	80050	80018	80053	80000	972201	1359983	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80035	587131	1360309	160085	20	80048	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240120	80030	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10

ST1 (multiple, post-index, 1 reg, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations