Icestorm: ST1 (multiple, post-index, 1 reg, 1D) measurements

Code:

  st1 { v0.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
61005	29600	2005	1003	1002	1002	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29117	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29115	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29138	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29416	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29469	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61005	29147	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29117	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29117	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0
61004	29115	2001	1001	1000	1000	1000	3000	4000	2000	1000	0	3000	1001	1000	0	0

Count: 8

Code:

  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8
  st1 { v0.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80147	160161	80143	80018	80143	80003	1123842	1359944	160109	200	80010	200	240030	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80205	80074	160141	80124	80017	80140	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80046	160102	80102	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100
80204	80039	160101	80101	80000	80104	80001	1060580	1359942	160105	200	80008	200	240024	80001	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80291	160073	80055	80018	80056	80000	948233	1360001	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80036	728096	1360313	160089	20	80048	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80035	648988	1360296	160086	20	80049	20	240000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	580309	1360047	160010	20	80000	20	240000	80001	80000	10

ST1 (multiple, post-index, 1 reg, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations