Icestorm: ST1 (multiple, post-index, 1 reg, 4H) measurements

Code:

  st1 { v0.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29664	2005	1003	1002	1002	1000	3000	4000	2000	1000	3000	1001	1000
61004	29045	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29076	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29074	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29068	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29074	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29082	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29017	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29064	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29043	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000

Count: 8

Code:

  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8
  st1 { v0.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80149	160158	80140	80018	80143	80003	1024943	1360026	160109	200	80010	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240153	80033	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80001	412130	1360102	160105	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80002	341231	1360107	160106	200	80008	200	240024	80004	80000	100
80204	80048	160104	80104	80000	80104	80001	412130	1360102	160105	200	80008	200	240024	80004	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80149	160073	80055	80018	80056	80003	812334	1360057	160019	20	80010	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240144	80033	80000	10
80024	80055	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80055	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10

ST1 (multiple, post-index, 1 reg, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations