Icestorm: ST1 (multiple, post-index, 1 reg, 8B) measurements

Code:

  st1 { v0.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29779	2013	1007	1006	1006	1000	3000	4000	2000	1000	3000	1001	1000
61004	29115	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29116	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29139	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29148	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29115	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29140	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29146	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29137	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000
61004	29119	2001	1001	1000	1000	1000	3000	4000	2000	1000	3000	1001	1000

Count: 8

Code:

  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8
  st1 { v0.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80147	160161	80143	80018	80143	80003	1123926	1359993	160109	200	80010	200	240030	80001	80000	100
80205	80095	160150	80133	80017	80140	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80066	160104	80104	80000	80104	80002	533162	1360071	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240144	80030	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100
80204	80045	160101	80101	80000	80104	80002	580838	1360053	160106	200	80008	200	240024	80001	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80026	80180	160108	80073	80035	80091	80002	420410	1360089	160016	20	80008	20	240000	80001	80000	10
80024	80047	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	420392	1360083	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80025	80080	160059	80042	80017	80052	80000	384566	1360209	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10
80024	80048	160011	80011	80000	80010	80000	340585	1360101	160010	20	80000	20	240000	80001	80000	10

ST1 (multiple, post-index, 1 reg, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations