Icestorm: ST1 (multiple, post-index, 2 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29817	3007	1003	2004	1002	2000	3000	8000	3000	2000	5000	1001	2000
62004	29584	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29629	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29824	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29864	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29646	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29571	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29583	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29595	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29589	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000

Count: 8

Code:

  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8
  st1 { v0.16b, v1.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	160146	240142	80124	160018	80123	160003	280291	2719932	240106	200	160010	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400120	80019	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100
160204	160045	240103	80103	160000	80102	160001	280273	2720010	240103	200	160008	200	400020	80003	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	160147	240051	80033	160018	80032	160003	280060	2719968	240016	20	160010	20	400120	80019	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160034	280128	2720120	240064	20	160048	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160025	160073	240046	80029	160017	80030	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	280041	2720007	240010	20	160000	20	400000	80001	160000	10

ST1 (multiple, post-index, 2 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations