Icestorm: ST1 (multiple, post-index, 2 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29677	3007	1003	2004	1002	2000	3000	8000	3000	2000	5000	1001	2000
62005	29370	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29341	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29362	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29365	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29339	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29339	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29341	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29365	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000
62004	29339	3001	1001	2000	1000	2000	3000	8000	3000	2000	5000	1001	2000

Count: 8

Code:

  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8
  st1 { v0.2d, v1.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	160271	240141	80123	160018	80122	160036	280363	2720850	240157	200	160050	200	400125	80021	160000	100
160204	160039	240103	80103	160000	80102	160036	280367	2719954	240157	200	160050	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160034	280355	2720194	240154	200	160048	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160204	160039	240103	80103	160000	80102	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100
160205	160090	240136	80119	160017	80120	160001	280275	2719886	240103	200	160008	200	400020	80003	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	160155	240052	80034	160018	80033	160000	280050	2719994	240010	20	160000	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160034	280130	2719996	240064	20	160048	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160025	160067	240046	80029	160017	80030	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160024	160040	240011	80011	160000	80010	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10
160024	160039	240011	80011	160000	80010	160396	281011	2735741	240626	20	160440	20	401425	80280	160000	10
160024	160374	240125	80071	160054	80070	160000	280043	2719883	240010	20	160000	20	400000	80001	160000	10

ST1 (multiple, post-index, 2 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations