Icestorm: ST1 (multiple, post-index, 2 regs, 2S) measurements

Code:

  st1 { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62006	29524	3007	1003	1002	1002	1002	1002	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29309	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29292	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29417	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29321	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29361	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29331	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29325	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29318	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000
62004	29294	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	2000	1001	1000	1000

Count: 8

Code:

  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8
  st1 { v0.2s, v1.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160206	80153	240186	80132	80036	80018	80138	80038	80004	1225124	1359990	320038	240122	200	80009	80009	200	240027	160018	80001	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160205	80105	240185	80131	80036	80018	80138	80038	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100
160204	80047	240107	80103	80004	80000	80106	80006	80002	520495	1360094	320026	240114	200	80006	80006	200	240018	160012	80003	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80151	240094	80041	80035	80018	80047	80037	80000	1024088	1360024	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160025	80097	240095	80041	80036	80018	80048	80038	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80068	240011	80011	80000	80000	80010	80000	80000	805766	1360081	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10
160024	80039	240011	80011	80000	80000	80010	80000	80000	1159959	1359955	320000	240010	20	80000	80000	20	240000	160000	80001	80000	80000	10

ST1 (multiple, post-index, 2 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations