Icestorm: ST1 (multiple, post-index, 3 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29560	4009	1003	3006	1002	3000	3000	12000	4000	3000	7000	1001	3000
63004	29307	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29317	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29305	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63005	29339	4005	1002	3003	1001	3000	3000	12000	4000	3000	7000	1001	3000
63004	29533	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29302	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29307	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29313	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29303	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	240155	320133	80115	240018	80114	240003	260307	4080004	320105	200	240010	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240035	260291	4080715	320147	200	240048	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560112	80013	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240034	260341	4080156	320147	200	240048	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100
240204	240047	320102	80102	240000	80101	240001	260303	4080046	320102	200	240008	200	560018	80002	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240026	240184	320071	80036	240035	80037	240003	260037	4080004	320015	20	240010	20	560000	80001	240000	10
240024	240039	320011	80011	240000	80010	240000	260030	4079883	320010	20	240000	20	560000	80001	240000	10
240024	240039	320011	80011	240000	80010	240000	260030	4079883	320010	20	240000	20	560018	80002	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560112	80013	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240037	260069	4080294	320061	20	240052	20	560000	80001	240000	10
240024	240065	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560120	80014	240000	10

ST1 (multiple, post-index, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations