Icestorm: ST1 (multiple, post-index, 3 regs, 1D) measurements

Code:

  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
63006	29726	4009	1003	1002	2004	1002	1002	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29339	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29296	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63005	29562	4004	1002	1000	2002	1001	1001	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29297	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29295	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29296	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29296	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29296	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000
63004	29296	4001	1001	1000	2000	1000	1000	2000	3000	12751	4000	4000	2000	1000	5000	2000	1001	2000	1000

Count: 8

Code:

  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240206	160152	320162	80122	80022	160018	80122	80023	160002	260334	2719956	320018	320109	200	160009	80005	200	400022	160010	80003	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160002	260331	2719858	320018	320109	200	160009	80005	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160045	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400120	160048	80023	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100
240204	160038	320104	80102	80002	160000	80102	80003	160001	260320	2719904	320013	320106	200	160008	80004	200	400020	160008	80002	160000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240026	160153	320072	80032	80022	160018	80032	80023	160000	260051	2719870	320000	320010	20	160000	80000	20	400120	160048	80023	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2720423	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160036	260126	2720369	320084	320088	20	160042	80021	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160038	260138	2720339	320102	320096	20	160049	80026	20	400000	160000	80001	160000	80000	10
240024	160039	320011	80011	80000	160000	80010	80000	160000	260044	2719919	320000	320010	20	160000	80000	20	400000	160000	80001	160000	80000	10

ST1 (multiple, post-index, 3 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations