Icestorm: ST1 (multiple, post-index, 3 regs, 2D) measurements

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29643	4021	1006	3015	1005	3000	3000	12000	4000	3000	7000	1001	3000
63004	29309	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63005	29324	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29307	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29292	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29292	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29300	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29299	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29301	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29296	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000

Count: 8

Code:

  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  st1 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	240145	320133	80115	240018	80114	240003	260307	4079932	320105	200	240010	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560112	80013	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240205	240073	320131	80114	240017	80114	240001	260303	4080316	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560112	80013	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240037	260306	4080132	320151	200	240052	200	560018	80002	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240026	240182	320072	80037	240035	80037	240001	260033	4080010	320012	20	240008	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560114	80014	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240033	260067	4080243	320055	20	240041	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560120	80014	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10
240024	240045	320011	80011	240000	80010	240000	260030	4080007	320010	20	240000	20	560000	80001	240000	10

ST1 (multiple, post-index, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations