Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 3 regs, 4S)

Test 1: uops

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
63005296714009100330061002300030001200040003000700010013000
63004294034001100130001000300030001200040003000700010013000
63004293584001100130001000300030001200040003000700010013000
63004293694001100130001000300030001200040003000700010013000
63004293824001100130001000300030001200040003000700010013000
63004294034001100130001000300030001200040003000700010013000
63004294424001100130001000300030001200040003000700010013000
63004303544001100130001000300030001200040003000700010013000
63004297534001100130001000300030001200040003000700010013000
63004293884001100130001000300030001200040003000700010013000

Test 2: throughput

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
2402062401843201618012624003580125240003260307407996832010520024001020056001880002240000100
2402042400473201038010324000080102240001260303408004632010220024000820056001880002240000100
2402042400473201028010224000080101240001260303408004632010220024000820056011280013240000100
2402042400473201028010224000080101240001260303408004632010220024000820056001880002240000100
2402042400473201028010224000080101240001260303408004632010220024000820056001880002240000100
2402052400753201318011424001780114240001260303408004632010220024000820056001880002240000100
2402042400473201028010224000080101240001260303408004632010220024000820056001880002240000100
2402042400473201028010224000080101240001260303408004632010220024000820056012080014240000100
2402042400473201028010224000080101240001260303408004632010220024000820056001880002240000100
2402042400473201028010224000080101240001260303408004632010220024000820056001880002240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
2400252402893200438002524001880024240001260033408001032001220240008205600008000124000010
2400242400453200118001124000080010240037260073408013232006120240052205600008000124000010
2400242400453200118001124000080010240000260030408000732001020240000205600008000124000010
2400242400453200118001124000080010240000260030408000732001020240000205600008000124000010
2400252400733200408002324001780024240000260030408000732001020240000205600008000124000010
2400242400523200118001124000080010240000260030408000732001020240000205600008000124000010
2400242400453200118001124000080010240000260030408000732001020240000205601118001224000010
2400242400453200118001124000080010240000260030408000732001020240000205600008000124000010
2400242400453200118001124000080010240000260030408000732001020240000205600008000124000010
2400252400733200418002424001780024240000260030408000732001020240000205600008000124000010