Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 3 regs, 8B)

Test 1: uops

Code:

  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63006297184009100310022004100210022000300012751400040002000100050002000100120001000
63004293954001100110002000100010002002300312761400440042002100150002000100120001000
63004293864001100110002000100010002000300012751400040002000100050002000100120001000
63004294094001100110002000100010002000300012751400040002000100050002000100120001000
63004294154001100110002000100010002000300012751400040002000100050002000100120001000
63004293884001100110002000100010002000300012751400040002000100050002000100120001000
63004293874001100110002000100010002000300012751400040002000100050002000100120001000
63004293874001100110002000100010002000300012751400040002000100050002000100120001000
63004294234001100110002000100010002000300012751400040002000100050002000100120001000
63004294194001100110002000100010002000300012751400040002000100050002000100120001000

Test 2: throughput

Count: 8

Code:

  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  st1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
240206160150320162801228002216001880122800231600022603342719992320018320109200160009800052004000201600088000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000201600088000216000080000100
240205160093320164801238002316001880123800241600012603172720074320013320106200160008800042004000201600088000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000121600068000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000201600088000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004001201600488002216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000201600088000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000201600088000216000080000100
240204160047320104801028000216000080102800031600012603172720074320013320106200160008800042004000201600088000216000080000100
240204160047320104801028000216000080102800031600372603962720524320093320182200160048800242004000201600088000216000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
240026160145320072800328002216001880032800231600002600482719971320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600412720161320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240025160083320075800338002416001880033800251600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010
240024160038320011800118000016000080010800001600002600442719901320000320010201600008000020400000160000800011600008000010