Icestorm: ST1 (multiple, post-index, 3 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29503	4009	1003	3006	1002	3000	3000	12000	4000	3000	7000	1001	3000
63004	29425	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29675	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29311	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29309	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29328	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29311	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29317	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29310	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000
63004	29323	4001	1001	3000	1000	3000	3000	12000	4000	3000	7000	1001	3000

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	240147	320134	80116	240018	80115	240003	260307	4079968	320105	200	240010	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240035	260327	4080074	320148	200	240049	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240205	240087	320129	80112	240017	80113	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560112	80013	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240204	240045	320102	80102	240000	80101	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100
240205	240073	320129	80112	240017	80113	240001	260303	4080010	320102	200	240008	200	560018	80002	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	240147	320043	80025	240018	80024	240036	260075	4080526	320060	20	240050	20	560018	80002	240000	10
240024	240037	320012	80012	240000	80011	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240025	240072	320040	80023	240017	80022	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240037	260074	4080114	320061	20	240052	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240025	240096	320040	80023	240017	80022	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10
240024	240037	320011	80011	240000	80010	240000	260030	4079847	320010	20	240000	20	560000	80001	240000	10

ST1 (multiple, post-index, 3 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations