Icestorm: ST1 (multiple, post-index, 4 regs, 16B) measurements

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	29863	5011	1003	4008	1002	4000	3000	16000	5000	4000	9000	1001	4000
64004	29558	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29568	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29571	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29527	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29532	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29559	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29580	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29920	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29570	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000

Count: 8

Code:

  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320206	320180	400155	80120	320035	80121	320003	240306	5440053	400105	200	320008	200	720018	80002	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720018	80002	320000	100
320204	320046	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720018	80002	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720108	80010	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720018	80002	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720108	80010	320000	100
320204	320053	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720018	80002	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720108	80010	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720018	80002	320000	100
320204	320039	400102	80102	320000	80102	320003	240306	5439893	400105	200	320008	200	720108	80010	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320025	320154	400040	80022	320018	80022	320036	240063	5440063	400057	20	320048	20	720018	80002	320000	10
320024	320037	400011	80011	320000	80010	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320025	320065	400037	80020	320017	80021	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320024	320037	400011	80011	320000	80010	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320025	320079	400037	80020	320017	80021	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320024	320037	400011	80011	320000	80010	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320025	320065	400037	80020	320017	80021	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320024	320037	400011	80011	320000	80010	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320025	320065	400037	80020	320017	80021	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10
320024	320037	400011	80011	320000	80010	320000	240030	5439847	400010	20	320000	20	720000	80001	320000	10

ST1 (multiple, post-index, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations