Icestorm: ST1 (multiple, post-index, 4 regs, 1D) measurements

Code:

  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
64006	29622	5011	1003	2004	2004	1002	2004	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29407	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29407	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29420	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29422	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29405	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29407	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29411	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	30184	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000
64004	29520	5001	1001	2000	2000	1000	2000	2000	3000	17751	8000	5000	2000	2000	5000	4000	1001	2000	2000

Count: 8

Code:

  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320206	160153	400185	80123	160044	160018	80123	160046	160002	240309	2720006	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320205	160092	400185	80123	160044	160018	80123	160046	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400120	320096	80023	160000	160000	100
320204	160054	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400020	320016	80003	160000	160000	100
320204	160047	400107	80103	160004	160000	80103	160006	160002	240309	2720105	640026	400111	200	160008	160008	200	400120	320096	80023	160000	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320026	160146	400095	80033	160044	160018	80033	160046	160002	240039	2720020	640026	400021	20	160008	160008	20	400020	320016	80003	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320025	160108	400095	80033	160044	160018	80033	160046	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10
320024	160045	400011	80011	160000	160000	80010	160000	160000	240030	2720063	640000	400010	20	160000	160000	20	400000	320000	80001	160000	160000	10

ST1 (multiple, post-index, 4 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations