Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, post-index, 4 regs, 4S)

Test 1: uops

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
64005305965024100640181005400030001600050004000900010014000
64004296605001100140001000400030001600050004000900010014000
64004296475001100140001000400030001600050004000900010014000
64004296425001100140001000400030001600050004000900010014000
64004296455001100140001000400030001600050004000900010014000
64004296835001100140001000400030001600050004000900010014000
64004296465001100140001000400030001600050004000900010014000
64004296505001100140001000400030001600050004000900010014000
64004296465001100140001000400030001600050004000900010014000
64004296465001100140001000400030001600050004000900010014000

Test 2: throughput

Count: 8

Code:

  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
3202053201524001308011232001880112320003240306543984440010520032000820072001880002320000100
3202053200814001278011032001780111320003240306543989340010520032000820072001880002320000100
3202043200394001028010232000080102320003240306543989340010520032000820072001880002320000100
3202053200674001278011032001780111320003240306543989340010520032000820072001880002320000100
3202043200394001028010232000080102320003240306543989340010520032000820072001880002320000100
3202053200674001278011032001780111320003240306543989340010520032000820072001880002320000100
3202043200394001028010232000080102320003240306543989340010520032000820072001880002320000100
3202043200544001028010232000080102320003240306543989340010520032000820072001880002320000100
3202043200394001028010232000080102320003240306543989340010520032000820072010880010320000100
3202043200394001028010232000080102320003240306543989340010520032000820072001880002320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
3200253201444000408002232001880022320003240036543980840001520320008207201088001032000010
3200243200374000118001132000080010320000240030543984740001020320000207200008000132000010
3200243200374000118001132000080010320000240030543984740001020320000207201088001032000010
3200243200374000118001132000080010320000240030543984740001020320000207200008000132000010
3200243200374000118001132000080010320036240063544009340005720320048207200008000132000010
3200243200374000118001132000080010320000240030543984740001020320000207200008000132000010
3200243200374000118001132000080010320036240063543996740005720320048207200008000132000010
3200243200374000118001132000080010320000240030543984740001020320000207200008000132000010
3200243200374000118001132000080010320036240063543996740005720320048207200188000232000010
3200243200394000118001132000080010320000240030543988340001020320000207200008000132000010