Icestorm: ST1 (multiple, post-index, 4 regs, 8H) measurements

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	30011	5024	1006	4018	1005	4000	3000	16000	5000	4000	9000	1001	4000
64004	29539	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29523	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29516	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29543	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29525	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29765	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29513	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29509	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000
64004	29509	5001	1001	4000	1000	4000	3000	16000	5000	4000	9000	1001	4000

Count: 8

Code:

  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320205	320146	400130	80112	320018	80112	320003	240306	5439919	400105	200	320008	200	720018	80002	320000	100
320205	320073	400127	80110	320017	80111	320003	240306	5439968	400105	200	320008	200	720018	80002	320000	100
320204	320045	400102	80102	320000	80102	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320205	320087	400127	80110	320017	80111	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320204	320045	400102	80102	320000	80102	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320205	320073	400127	80110	320017	80111	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320204	320045	400102	80102	320000	80102	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320205	320073	400127	80110	320017	80111	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320204	320045	400102	80102	320000	80102	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100
320205	320087	400127	80110	320017	80111	320003	240306	5440017	400105	200	320008	200	720018	80002	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320025	320150	400040	80022	320018	80022	320003	240036	5440004	400015	20	320008	20	720108	80010	320000	10
320024	320039	400012	80012	320000	80012	320003	240036	5439893	400015	20	320008	20	720018	80002	320000	10
320024	320039	400012	80012	320000	80012	320000	240030	5439883	400010	20	320000	20	720108	80010	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5439883	400010	20	320000	20	720000	80001	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5440097	400010	20	320000	20	720108	80010	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5439883	400010	20	320000	20	720000	80001	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5439883	400010	20	320000	20	720090	80009	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5439883	400010	20	320000	20	720000	80001	320000	10
320024	320039	400011	80011	320000	80010	320036	240063	5440003	400057	20	320048	20	720000	80001	320000	10
320024	320039	400011	80011	320000	80010	320000	240030	5439883	400010	20	320000	20	720000	80001	320000	10

ST1 (multiple, post-index, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations