Icestorm: ST1 (single, post-index, B) measurements

Code:

  st1 { v0.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62006	29601	3007	1003	1002	1002	1002	1002	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29420	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29407	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29407	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29419	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29423	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29578	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29592	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29407	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000
62004	29426	3001	1001	1000	1000	1000	1000	1000	3000	8751	4000	3000	1000	1000	3000	1000	1001	1000	1000

Count: 8

Code:

  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8
  st1 { v0.b }[1], [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160206	80146	240186	80131	80037	80018	80139	80039	80004	1223431	1359954	320038	240122	200	80009	80009	200	240018	80006	80001	80000	80000	100
160204	80045	240108	80101	80007	80000	80109	80009	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80005	80000	80000	100
160205	80108	240185	80131	80036	80018	80138	80038	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160204	80045	240105	80101	80004	80000	80106	80006	80002	680436	1360058	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100
160205	80104	240185	80131	80036	80018	80138	80038	80002	420855	1360184	320026	240114	200	80006	80006	200	240018	80006	80001	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80145	240093	80041	80034	80018	80046	80036	80033	1413429	1360361	320150	240117	20	80037	80037	20	240024	80008	80002	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80032	1595295	1360649	320146	240114	20	80036	80036	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	680159	1360052	320000	240010	20	80000	80000	20	240000	80000	80001	80000	80000	10

ST1 (single, post-index, B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations