Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (single, post-index, S)

Test 1: uops

Code:

  st1 { v0.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200629684300710031002100210021002100030008751400030001000100030001000100110001000
6200429459300110011000100010001000100030008751400030001000100030001000100110001000
6200429403300110011000100010001000100030008751400030001000100030001000100110001000
6200429437300110011000100010001000100030008751400030001000100030001000100110001000
6200429409300110011000100010001000100030008751400030001000100030001000100110001000
6200429405300110011000100010001000100030008751400030001000100030001000100110001000
6200429461300110011000100010001000100030008751400030001000100030001000100110001000
6200429377300110011000100010001000100030008751400030001000100030001000100110001000
6200429377300110011000100010001000100030008751400030001000100030001000100110001000
6200429461300110011000100010001000100030008751400030001000100030001000100110001000

Test 2: throughput

Count: 8

Code:

  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  st1 { v0.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1602078020424026380161800668003680168800688000411003501360003320038240122200800098000920024002780009800018000080000100
1602048004524010580101800048000080106800068003313136121360394320150240207200800378003720024001880006800018000080000100
160204800452401058010180004800008010680006800026804361360058320026240114200800068000620024001880006800018000080000100
160205801042401838013180034800188013680036800026804361360058320026240114200800068000620024011480038800318000080000100
160204800452401058010180004800008010680006800026804361360058320026240114200800068000620024001880006800018000080000100
160205801032401838013180034800188013680036800026804361360058320026240114200800068000620024001880006800018000080000100
160204800452401058010180004800008010680006800339902131360419320154240209200800388003820024001880006800018000080000100
160204800522401098010580004800008010680006800026804361360058320026240114200800068000620224011180037800318000080000100
160204800522401098010580004800008010680006800026804361360058320026240114200800068000620024001880006800018000080000100
160204800452401058010180004800008010680006800026804361360058320026240114200800068000620024001880006800018000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160026801512400938004180034800188004680036800025202701360094320026240024208000680006202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600248005424001180011800008000080010800008000011175031359973320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600258010024009580041800368001880048800388000011599591359955320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010
1600248003924001180011800008000080010800008000011599591359955320000240010208000080000202400008000080001800008000010