Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST2 (multiple, post-index, 4H)

Test 1: uops

Code:

  st2 { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200629576300710031002100210021002100030008751400030001000100030002000100110001000
6200429334300110011000100010001000100030008751400030001000100030002000100110001000
6200429340300110011000100010001000100030008751400030001000100030002000100110001000
6200429382300110011000100010001000100030008751400030001000100030002000100110001000
6200429338300110011000100010001000100030008751400030001000100030002000100110001000
6200429334300110011000100010001000100030008751400030001000100030002000100110001000
6200429335300110011000100010001000100030008751400030001000100030002000100110001000
6200429390300110011000100010001000100030008751400030001000100030002000100110001000
6200429368300110011000100010001000100030008751400030001000100030002000100110001000
6200429335300110011000100010001000100030008751400030001000100030002000100110001000

Test 2: throughput

Count: 8

Code:

  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  st2 { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680293240185801318003680018801388003880004122340313599393200382401222008000980009200240018160012800018000080000100
1602048004524010880101800078000080109800098000268043613600583200262401142008000680006200240018160012800018000080000100
16020480045240105801018000480000801068000680033122464613604193201542402092008003880038200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
1602048004524010580101800048000080106800068000268043613600583200262401142008000680006200240018160012800018000080000100
16020480045240105801018000480000801068000680033110334813604113201542402092008003880038200240018160012800058000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1600268015324009580041800368001880048800388000052024113600883200002400102080000800002024000016000080001800008000010
1600248004724001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010
1600248005024001980015800048000080016800068000090411213600393200002400102080000800002024000016000080001800008000010
1600248004724001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010
1600248004724001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010
1600248003524001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010
1600248005624001180011800008000080010800008000045167813601063200002400102080000800002024000016000080001800008000010
1600248004724001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010
1600258010624009580041800368001880048800388000052024113600883200002400102080000800002024000016000080001800008000010
1600248004724001180011800008000080010800008000052024113600883200002400102080000800002024000016000080001800008000010