Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (multiple, 4S)

Test 1: uops

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6600829930601313006300630063000250021200060003000300060009000130003000
6600429828600113000300030003000250021200060003000300060009000130003000
6600429697600113000300030003000250021200060003000300060009000130003000
6600429734600113000300030003000250021200060003000300060009000130003000
6600429699600113000300030003000250021200060003000300060009000130003000
6600429698600113000300030003000250021200060003000300060009000130003000
6600429698600113000300030003000250021200060003000300060009000130003000
6600429717600113000300030003000250021200060003000300060009000130003000
6600429700600113000300030003000250021200060003000300060009000130003000
6600429698600113000300030003000250021200060003000300060009000130003000

Test 2: throughput

Count: 8

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  st3 { v0.4s, v1.4s, v2.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48020824015048016710124004824001810024005024000230040797389600344801102002400072400092004800147200271240000240000100
48020524008048016710124004824001810024005024000230040798929600344801102002400072400092004800147200271240000240000100
48020424003948010710124000624000010024000824000230040798929600344801102002400072400092004800147200271240000240000100
48020424003948010710124000624000010024000824000230040798929600344801102002400072400092004801007201621240000240000100
48020424003948010710124000624000010024000824000330040707599600394801122002400092400092004800147200271240000240000100
48020424003948010710124000624000010024000824000230040798929600344801102002400072400092004800147200271240000240000100
48020424003948010710124000624000010024000824003830040801539602024801882002400502400542004800147200271240000240000100
48020424003948010710124000624000010024000824000230040798929600344801102002400072400092004800147200271240000240000100
48020424003948010710124000624000010024000824000230040798929600344801102002400072400092004800147200271240000240000100
48020524008048016710124004824001810024005024000230040798929600344801102002400072400092004800147200271240000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
48002824015248007711240048240018102400502400383040802909602024800982024005024005420480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010
48002524008648007711240048240018102400502400003040800239600004800102024000024000020480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480100720162124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010
48002524010948007711240048240018102400502400003040800239600004800102024000024000020480000720000124000024000010
48002424004548001111240000240000102400002400003040800239600004800102024000024000020480000720000124000024000010