Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (multiple, post-index, 16B)

Test 1: uops

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
660082984970151003300630061002300630003000250001200070003000300070009000100130003000
660042958970011001300030001000300030003000250001200070003000300070009000100130003000
660042958870011001300030001000300030003000250001200070003000300070009000100130003000
660042956570011001300030001000300030003000250001200070003000300070009000100130003000
660042958870011001300030001000300030003000250001200070003000300070009000100130003000
660042959270011001300030001000300030003000250001200070003000300070009000100130003000
660042956670011001300030001000300030003000250001200070003000300070009000100130003000
660042961270011001300030001000300030003000250001200070003000300070009000100130003000
660042956870011001300030001000300030003000250001200070003000300070009000100130003000
660042956570011001300030001000300030003000250001200070003000300070009000100130003000

Test 2: throughput

Count: 8

Code:

  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  st3 { v0.16b, v1.16b, v2.16b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4802082401465601828011624004824001880116240050240002240306407977996003456011220024000724000920056001672002780002240000240000100
4802052400815601828011624004824001880116240050240002240306407993396003456011220024000724000920056001672002780002240000240000100
4802042400415601088010224000624000080102240008240002240306407993396003456011220024000724000920056001672002780002240000240000100
4802042400415601088010224000624000080102240008240038240348408052396020256020420024005024005420056001672002780002240000240000100
4802042400415601088010224000624000080102240008240002240306407993396003456011220024000724000920056011672016280016240000240000100
4802042400485601088010224000624000080102240008240002240306407993396003456011220024000724000920056001672002780002240000240000100
4802052400825601828011624004824001880116240050240002240306407993396003456011220024000724000920056001672002780002240000240000100
4802042400415601088010224000624000080102240008240002240306407993396003456011220024000724000920056001672002780002240000240000100
4802042400415601088010224000624000080102240008240002240306407993396003456011220024000724000920056011672016280016240000240000100
4802042400415601088010224000624000080102240008240002240306407993396003456011220024000724000920056001672002780002240000240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
4800292401865601668004024009024003680040240092240002240036407998896003456002220240007240009205600167200278000224000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205600007200008000124000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205601167201628001624000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205600007200008000124000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205600007200008000124000024000010
4800252400825600928002624004824001880026240050240000240030407992796000056001020240000240000205600007200008000124000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205600007200008000124000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205601167201628001624000024000010
4800242400415600118001124000024000080010240000240000240030407992796000056001020240000240000205600007200008000124000024000010
4800242400415600118001124000024000080010240000240144240198408536496067256037820240172240180205600007200008000124000024000010