Icestorm: ST3 (multiple, post-index, 4S) measurements

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 3.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66008	30133	7015	1003	3006	3006	1002	3006	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29749	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29704	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	30442	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29745	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29697	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29743	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29742	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	30164	7001	1001	3000	3000	1000	3000	3000	3000	25000	12000	7000	3000	3000	7000	9000	1001	3000	3000
66004	29745	7001	1001	3000	3000	1000	3000	3002	3001	25004	12005	7006	3003	3003	7000	9000	1001	3000	3000

Count: 8

Code:

  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8
  st3 { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 3.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480208	240159	560182	80116	240048	240018	80116	240050	240002	240306	4079738	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240039	560108	80102	240006	240000	80102	240008	240038	240348	4080212	960202	560204	200	240050	240054	200	560016	720027	80002	240000	240000	100
480205	240087	560183	80117	240048	240018	80116	240051	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240039	560108	80102	240006	240000	80102	240008	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480205	240080	560182	80116	240048	240018	80116	240050	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240039	560108	80102	240006	240000	80102	240008	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240039	560108	80102	240006	240000	80102	240008	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240039	560108	80102	240006	240000	80102	240008	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480204	240047	560108	80102	240006	240000	80102	240008	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100
480205	240099	560182	80116	240048	240018	80116	240050	240002	240306	4079892	960034	560112	200	240007	240009	200	560016	720027	80002	240000	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480028	240151	560092	80026	240048	240018	80026	240050	240002	240036	4079988	960034	560022	20	240007	240009	20	560016	720027	80002	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480025	240085	560085	80025	240042	240018	80024	240042	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560116	720162	80016	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240038	240078	4080542	960202	560114	20	240050	240054	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10
480024	240045	560011	80011	240000	240000	80010	240000	240000	240030	4080023	960000	560010	20	240000	240000	20	560000	720000	80001	240000	240000	10

ST3 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations