Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (single, D)

Test 1: uops

Code:

  st3 { v0.d, v1.d, v2.d }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
640072973140091200420042004200017253800040002000200040006000120002000
640042951540011200020002000200017253800040002000200040006000120002000
640042952640011200020002000200017253800040002000200040006000120002000
640042949240011200020002000200017253800040002000200040006000120002000
640042952140011200020002000200017253800040002000200040006000120002000
640042948540011200020002000200017253800040002000200040006000120002000
640042953840011200020002000200017253800040002000200040006000120002000
640042948940011200020002000200017253800040002000200040006000120002000
640042947440011200020002000200017253800040002000200040006000120002000
640043004340011200020002000200017253800040002000200040006000120002000

Test 2: throughput

Count: 8

Code:

  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  st3 { v0.d, v1.d, v2.d }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
32020816019132022310116008616003610016008816000230027200206400263201082001600081600082003200164800241160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200164800241160000160000100
32020416003932010510116000416000010016000616000230027199436400263201082001600081600082003200164800241160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200164800241160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200164800241160000160000100
32020516008332016310116004416001810016004616000230027199436400263201082001600081600082003200164800241160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200964801441160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200164800241160000160000100
32020416003832010510116000416000010016000616000230027199436400263201082001600081600082003200964801441160000160000100
32020516009632016310116004416001810016004616000230027199436400263201082001600081600082003200164800241160000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
32002816019732013311160086160036101600881600023027201956400263200182016000816000820320000480000116000016000010
32002416004532001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416004532001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320096480144116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010
32002416003832001111160000160000101600001600003027199376400003200102016000016000020320000480000116000016000010