Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST3 (single, H)

Test 1: uops

Code:

  st3 { v0.h, v1.h, v2.h }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
62006295222005110021002100210008751400020001000100020003000110001000
62004293002001110001000100010008751400020001000100020003000110001000
62004293012001110001000100010008751400020001000100020003000110001000
62004293012001110001000100010008751400020001000100020003000110001000
62004293002001110001000100010008751400020001000100020003000110001000
62004293042001110001000100010008751400020001000100020003000110001000
62004293022001110001000100010008751400020001000100020003000110001000
62004293012001110001000100010008751400020001000100020003000110001000
62004294982001110001000100010008751400020001000100020003000110001000
62004293012001110001000100010008751400020001000100020003000110001000

Test 2: throughput

Count: 8

Code:

  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  st3 { v0.h, v1.h, v2.h }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680293160156101800378001810080039800013001359868320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020580097160153101800348001810080036800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100
16020480038160105101800048000010080006800013001359940320026160107200800068000620016001224001818000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002680147160065118003680018108003880001301360102320026160017208000680006201600122400181800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600122400181800008000010
16002580104160063118003480018108003680000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600002400001800008000010
16002580105160063118003480018108003680000301359955320000160010208000080000201600002400001800008000010