Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (multiple, 16B)

Test 1: uops

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
7200730020120251801640088016400044011400001200040008000800020000140008000
7200429895120011800040008000400044015400001200040008000800020000140008000
7200429892120011800040008000400044015400001200040008000800020000140008000
7200429890120011800040008000400044015400001200040008000800020000140008000
7200429880120011800040008000400044015400001200040008000800020000140008000
7200429929120011800040008000400044015400001200040008000800020000140008000
7200429893120011800040008000400044015400001200040008000800020000140008000
7200429898120011800040008000400044015400001200040008000800020000140008000
7200429894120011800040008000400044015400001200040008000800020000140008000
7200429932120011800040008000400044015400001200040008000800820020140008000

Test 2: throughput

Count: 8

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
9602073201549602071016400883200181006401003200063003935166320005196011620032000664001420064001216000351320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064008416002151320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064001216000351320000640000100
9602043200429601051016400043200001006400103200023004941527320005196011220032000664001420064008416002151320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064001216000351320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064008416002151320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064001216000351320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064008016002101320000640000100
9602043200429601051016400043200001006400103200393004502996320037096021720032004264008620064001216000351320000640000100
9602043200429601051016400043200001006400103200063004560008320005196011620032000664001420064001216000351320000640000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
9600273202849601231164009432001810640100320000304559979320000096001020320000640000206400001600000132000064000010
9600243200429600111164000032000010640000320042304060274320037096013020320042640086206400001600000132000064000010
9600243200429600111164000032000010640000320000304559979320000096001020320000640000206400001600000132000064000010
9600243200429600111164000032000010640000320036305033416320031996011420320036640072206400001600000132000064000010
9600243200429600111164000032000010640000320000304559979320000096001020320000640000206400001600000132000064000010
9600253200899600911164006232001810640078320000304559979320000096001020320000640000206400001600000132000064000010
9600243200429600111164000032000010640000320000304559979320000096001020320000640000206400001600000132000064000010
9600253200969600941164006232002110640078320000304559979320000096001020320000640000206400001600000132000064000010
9600243200429600111164000032000010640000320000304559979320000096001020320000640000206400001600000132000064000010
9600253200889600911164006232001810640078320000304559979320000096001020320000640000206400001600000132000064000010