Icestorm: ST4 (multiple, 16B) measurements

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72007	30020	12025	1	8016	4008	8016	4000	44011	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29895	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29892	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29890	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29880	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29929	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29893	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29898	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29894	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29932	12001	1	8000	4000	8000	4000	44015	40000	12000	4000	8000	8008	20020	1	4000	8000

Count: 8

Code:

  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960207	320154	960207	101	640088	320018	100	640100	320006	300	3935166	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640084	1600215	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320002	300	4941527	3200051	960112	200	320006	640014	200	640084	1600215	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640084	1600215	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640080	1600210	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320039	300	4502996	3200370	960217	200	320042	640086	200	640012	1600035	1	320000	640000	100
960204	320042	960105	101	640004	320000	100	640010	320006	300	4560008	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960027	320284	960123	11	640094	320018	10	640100	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320042	30	4060274	3200370	960130	20	320042	640086	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320036	30	5033416	3200319	960114	20	320036	640072	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320089	960091	11	640062	320018	10	640078	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320096	960094	11	640062	320021	10	640078	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320042	960011	11	640000	320000	10	640000	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320088	960091	11	640062	320018	10	640078	320000	30	4559979	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10

ST4 (multiple, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations