Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (multiple, 2S)

Test 1: uops

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 6.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
66007298906013140082004400820002125719502600020004000400010000120004000
66004298396001140002000400020002125719502600020004000400410010120004000
66004296976001140002000400020002125719502600020004000400010000120004000
66004297066001140002000400020002125719502600020004000400010000120004000
66004296596001140002000400020002125919504600020004000400010000120004000
66004297276001140002000400020002185019502600020004000400010000120004000
66004296676001140002000400020002125719502600020004000400010000120004000
66004296516001140002000400020002125719502600020004000400010000120004000
66004296976001140002000400020002125919504600020004000400010000120004000
66004296566001140002000400020002125719502600020004000400010000120004000

Test 2: throughput

Count: 8

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
480207160276480215101320091160023100320097160007300177587016000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160043300240082716004644802372001600473200952003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160041300226079616004644802352001600473200952003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480204160045480109101320008160000100320014160007300255954716000714801212001600073200152003200148000371160000320000100
480205160095480206101320082160023100320094160007300255954716000714801212001600073200152003200148000371160000320000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
480027160151480122113200881600231032009716000030271992616000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320080800204116000032000010
480024160046480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320080800204116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016000030175999516000004800102016000032000020320000800000116000032000010
480024160039480011113200001600001032000016004030176036416003804801302016004032008220320000800000116000032000010