Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (multiple, 4S)

Test 1: uops

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
7200730171120251801640088016400044003400001200040008000800020000140008000
7200429912120011800040008000400044003400001200040008000800020000140008000
7200429916120011800040008000400044003400001200040008000800020000140008000
7200429916120011800040008000400044003400001200040008000800020000140008000
7200429910120011800040008000400044003400001200040008000800020000140008000
7200429913120011800040008000400044003400001200040008000800020000140008000
7200429914120011800040008000400044003400001200040008000800020000140008000
7200429920120011800040008000400244005400061200640028004800020000140008000
7200430116120011800040008000400044003400001200040008000800020000140008000
7200429916120011800040008000400044003400001200040008000800020000140008000

Test 2: throughput

Count: 8

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
9602073201389602071016400883200181006401003200063003950379320005196011620032000664001420064001216000351320000640000100
9602043200509601051016400043200001006400103200063004831981320005196011620032000664001420064009816002471320000640000100
9602043200509601071016400063200001006400123200023005439962320006196011420032000864001620064001616000401320000640000100
9602043200509601071016400063200001006400123200023005439962320006196011420032000864001620064009816002471320000640000100
9602043200509601071016400063200001006400123200023005439962320006196011420032000864001620064001616000401320000640000100
9602043200509601071016400063200001006400123200383005440467320047196023320032004964009920064001616000401320000640000100
9602043200509601071016400063200001006400123200023005439962320006196011420032000864001620064001616000401320000640000100
9602043200509601071016400063200001006400123200383005440467320047196023320032004964009920064001616000401320000640000100
9602043200509601071016400063200001006400123200023005439962320006196011420032000864001620064001616000401320000640000100
9602043200509601071016400063200001006400123200383005440701320047696023520032004964009920064001616000401320000640000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
9600273201449601211164009232001810640100320000304223941320000096001020320000640000206400001600000132000064000010
9600253200899601001164006832002110640084320000305439945320000096001020320000640000206400001600000132000064000010
9600243200459600111164000032000010640000320000305439945320000096001020320000640000206400001600000132000064000010
9600253200999600991164007032001810640086320000305439945320000096001020320000640000206400001600000132000064000010
9600243200459600111164000032000010640000320000305439945320000096001020320000640000206400881600230132000064000010
9600243200459600111164000032000010640000320000305439945320000096001020320000640000206400001600000132000064000010
9600243200459600111164000032000010640000320000305439945320000096001020320000640000206400881600230132000064000010
9600243200459600111164000032000010640000320000305439945320000096001020320000640000206400881600230132000064000010
9600243200689600111164000032000010640000320000305439945320000096001020320000640000206400921600235132000064000010
9600243200459600111164000032000010640000320005305439979320005196002520320006640014206400121600035132000064000010