Icestorm: ST4 (multiple, 4S) measurements

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72007	30171	12025	1	8016	4008	8016	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29912	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29916	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29916	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29910	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29913	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29914	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29920	12001	1	8000	4000	8000	4002	44005	40006	12006	4002	8004	8000	20000	1	4000	8000
72004	30116	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29916	12001	1	8000	4000	8000	4000	44003	40000	12000	4000	8000	8000	20000	1	4000	8000

Count: 8

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960207	320138	960207	101	640088	320018	100	640100	320006	300	3950379	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320050	960105	101	640004	320000	100	640010	320006	300	4831981	3200051	960116	200	320006	640014	200	640098	1600247	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320002	300	5439962	3200061	960114	200	320008	640016	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320002	300	5439962	3200061	960114	200	320008	640016	200	640098	1600247	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320002	300	5439962	3200061	960114	200	320008	640016	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320038	300	5440467	3200471	960233	200	320049	640099	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320002	300	5439962	3200061	960114	200	320008	640016	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320038	300	5440467	3200471	960233	200	320049	640099	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320002	300	5439962	3200061	960114	200	320008	640016	200	640016	1600040	1	320000	640000	100
960204	320050	960107	101	640006	320000	100	640012	320038	300	5440701	3200476	960235	200	320049	640099	200	640016	1600040	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960027	320144	960121	11	640092	320018	10	640100	320000	30	4223941	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320089	960100	11	640068	320021	10	640084	320000	30	5439945	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320099	960099	11	640070	320018	10	640086	320000	30	5439945	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640088	1600230	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640088	1600230	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640088	1600230	1	320000	640000	10
960024	320068	960011	11	640000	320000	10	640000	320000	30	5439945	3200000	960010	20	320000	640000	20	640092	1600235	1	320000	640000	10
960024	320045	960011	11	640000	320000	10	640000	320005	30	5439979	3200051	960025	20	320006	640014	20	640012	1600035	1	320000	640000	10

ST4 (multiple, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations