Icestorm: ST4 (multiple, 8H) measurements

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 12.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72007	30251	12025	1	8016	4008	8016	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29955	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29917	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29916	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29915	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29923	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29958	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29934	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29915	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000
72004	29917	12001	1	8000	4000	8000	4000	44014	40000	12000	4000	8000	8000	20000	1	4000	8000

Count: 8

Code:

  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960207	320148	960206	101	640084	320021	100	640096	320006	300	3980770	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320042	300	4857250	3200400	960226	200	320044	640092	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320006	300	5439973	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320042	300	4736103	3200400	960226	200	320044	640092	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320006	300	5439973	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320038	300	5440753	3200430	960228	200	320048	640096	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320006	300	5439973	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960205	320093	960189	101	640070	320018	100	640086	320006	300	5439973	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960204	320045	960105	101	640004	320000	100	640010	320006	300	5439973	3200051	960116	200	320006	640014	200	640012	1600035	1	320000	640000	100
960205	320092	960187	101	640068	320018	100	640084	320006	300	5439973	3200051	960116	200	320006	640014	200	640016	1600040	1	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960028	320188	960216	11	640166	320039	10	640179	320005	30	5439979	3200051	960025	20	320006	640014	20	640000	1600000	1	320000	640000	10
960024	320046	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320091	960104	11	640072	320021	10	640088	320000	30	5440264	3200087	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320046	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320090	960102	11	640070	320021	10	640086	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320046	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960025	320090	960102	11	640070	320021	10	640086	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320046	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640094	1600242	1	320000	640000	10
960024	320053	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640000	1600000	1	320000	640000	10
960024	320046	960011	11	640000	320000	10	640000	320000	30	5439958	3200000	960010	20	320000	640000	20	640094	1600242	1	320000	640000	10

ST4 (multiple, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations