Icestorm: ST4 (multiple, post-index, 2S) measurements

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66007	29683	7015	1003	4008	2004	1002	4008	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29526	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29524	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29521	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29542	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29541	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29521	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66005	29562	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29526	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29545	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000

Count: 8

Code:

  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480208	160192	560348	80143	320167	160038	80143	320174	160007	240309	1784302	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160053	560116	80103	320008	160005	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400099	800204	80018	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160040	240356	1760275	1600380	560239	200	160040	320082	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480027	160145	560139	80033	320088	160018	80033	320094	160000	240030	1759997	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	2656705	1630266	560010	20	160000	320000	20	400500	801000	80101	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400200	800400	80041	160000	320000	10
480024	161612	561309	80231	320880	160198	80230	320880	160396	240690	1791369	1607190	561506	20	160440	320880	20	400500	801000	80101	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480025	160087	560115	80028	320064	160023	80029	320080	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160039	560011	80011	320000	160000	80010	320000	160000	240030	1759996	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10

ST4 (multiple, post-index, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations