Icestorm: ST4 (multiple, post-index, 4H) measurements

Code:

  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66007	29765	7015	1003	4008	2004	1002	4008	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29647	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29649	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29636	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29634	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29647	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29648	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29632	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29634	7001	1001	4000	2000	1000	4000	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29634	7001	1001	4000	2000	1000	4000	2000	3000	21257	19502	7000	2000	4000	5005	10010	1002	2000	4000

Count: 8

Code:

  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480207	160147	560229	80123	320088	160018	80123	320094	160007	240309	1759942	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160053	560116	80103	320008	160005	80103	320014	160040	240356	1760264	1600380	560239	200	160040	320082	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160053	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480205	160087	560205	80118	320064	160023	80119	320080	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160041	560111	80103	320008	160000	80103	320014	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480205	160087	560205	80118	320064	160023	80119	320080	160007	240309	1759941	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480027	160540	560139	80033	320088	160018	80033	320094	160036	240090	1803493	1600400	560146	20	160040	320080	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480025	160123	560138	80033	320087	160018	80033	320094	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400117	800237	80023	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10

ST4 (multiple, post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations