Icestorm: ST4 (multiple, post-index, 4S) measurements

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 12.000

Issues: 13.000

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 8.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
72007	30261	13027	1003	8016	4008	1002	8016	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29893	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29891	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29890	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29930	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29888	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72005	29958	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29932	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29933	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000
72004	29911	13001	1001	8000	4000	1000	8000	4000	3000	44010	40000	13000	4000	8000	9000	20000	1001	4000	8000

Count: 8

Code:

  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960207	320148	1040217	80112	640084	320021	80111	640096	320006	240303	3965581	3200051	1040117	200	320006	640014	200	720013	1600035	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320039	240333	5109820	3200461	1040243	200	320047	640097	200	720018	1600040	80002	320000	640000	100
960204	320050	1040108	80102	640006	320000	80101	640012	320002	240303	5439962	3200061	1040115	200	320008	640016	200	720018	1600040	80002	320000	640000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
960027	320136	1040126	80022	640086	320018	80021	640100	320000	240030	4375954	3200000	1040010	20	320000	640000	20	720105	1600242	80011	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320042	240063	5225356	3200456	1040156	20	320047	640097	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320042	240063	4913547	3200456	1040156	20	320047	640097	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320042	240063	4662328	3200461	1040156	20	320047	640097	20	720000	1600000	80001	320000	640000	10
960024	320050	1040011	80011	640000	320000	80010	640000	320000	240030	5439956	3200000	1040010	20	320000	640000	20	720000	1600000	80001	320000	640000	10

ST4 (multiple, post-index, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations