Icestorm: ST4 (multiple, post-index, 8B) measurements

Code:

  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 6.000

Issues: 7.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 4.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
66007	29785	7015	1003	4008	2004	1002	4008	2000	3000	21256	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29584	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29566	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29570	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29566	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29562	7001	1001	4000	2000	1000	4000	2000	3000	21257	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29810	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	30286	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10002	1001	2000	4000
66004	29575	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000
66004	29563	7001	1001	4000	2000	1000	4000	2000	3000	21252	19502	7000	2000	4000	5000	10000	1001	2000	4000

Count: 8

Code:

  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
  st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480208	160347	560330	80139	320150	160041	80141	320166	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160007	240309	1999887	1600071	560124	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480205	160111	560233	80123	320087	160023	80123	320094	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400117	800237	80023	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100
480204	160047	560111	80103	320008	160000	80103	320014	160006	240309	2719954	1600071	560123	200	160007	320015	200	400017	800037	80003	160000	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
480027	160142	560139	80033	320088	160018	80033	320094	160003	240039	2719990	1600071	560030	20	160007	320015	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160043	240099	2316278	1600471	560170	20	160047	320095	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480025	160099	560138	80033	320087	160018	80033	320094	160000	240030	2720052	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10
480024	160047	560011	80011	320000	160000	80010	320000	160000	240030	2719926	1600000	560010	20	160000	320000	20	400000	800000	80001	160000	320000	10

ST4 (multiple, post-index, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations