Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, S)

Test 1: uops

Code:

  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
63007320753022120141007201410001050297503000100020000200050001100020000
63004296043001120001000200010001050297503000100020000200050001100020000
63004296353001120001000200010001050297503000100020000200050001100020000
63004292963001120001000200010001050297503000100020000200050001100020000
63004292993001120001000200010001050297503000100020000200050001100020000
63004293383001120001000200010001050297503000100020000200050001100020000
630042936430011200010002000100010502975030001000200018722196209591010718391133
63004302253001120001000200010001050297503000100020000200050001100020000
63004292983001120001000200010001050297503000100020000200050001100020000
63004293363001120001000200010001050297503000100020000200050001100020000

Test 2: throughput

Count: 8

Code:

  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  st4 { v0.s, v1.s, v2.s, v3.s }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24020780166240185101160066800181001600728000630099517980005124011620080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160074400187180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100
240204800502401071011600068000010016001280002300135996280006124011420080006160014200160012400035180000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
240027801392400951116006680018101600728000630113197080005124002620800061600142016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016007240019018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016000040000018000016000010
240024800452400111116000080000101600008000030135994580000024001020800001600002016007440018718000016000010