Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, post-index, B)

Test 1: uops

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
63007297504009100320041002100220041000300010502975140001000200030005000100110002000
63004294524001100120001000100020001000300010501975140001000200030005000100110002000
63004294734001100120001000100020001000300010501975140001000200030005000100110002000
63004294774001100120001000100020001000300010501975140001000200030005000100110002000
63004294504001100120001000100020001000300010501975140001000200030005000100110002000
63004294524001100120001000100020001000300010501975140001000200030005000100110002000
63004294754001100120001000100020001000300010501975140001000200030005000100110002000
63004294964001100120001000100020001000300010501975140001000200030005000100110002000
63004294774001100120001000100020001000300010501975140001000200030005000100110002000
63004294504001100120001000100020001000300010501975140001000200030005000100110002000

Test 2: throughput

Count: 8

Code:

  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  st4 { v0.b, v1.b, v2.b, v3.b }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
2402078050432021880134160066800188013616007280006340328991359800051320122200800071600152002400214000378000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020580107320222801351600668002180136160072800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800023392961360066800061320120200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100
24020480044320109801051600048000080106160010800063403321295282800051320122200800061600142002400184000358000580000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
24002780146320128800441600668001880046160072800063400471169990800051320032208000716001520240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480054320011800111600008000080010160000800003323811360091800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010
24002480047320011800111600008000080010160000800003400271359965800000320010208000016000020240000400000800018000016000010