Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST4 (single, post-index, D)

Test 1: uops

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
64007296945011100320042004100220042000300017251800050002000200050004000100120002000
64004294335001100120002000100020002000300017251800050002000200050004000100120002000
64004299305001100120002000100020002000300017251800050002000200050004000100120002000
64004296965001100120002000100020002000300017251800050002000200050004000100120002000
64004294685001100120002000100020002000300017251800050002000200050004000100120002000
64004294865001100120002000100020002000300017251800050002000200050004000100120002000
64004294785001100120002000100020002000300017251800050002000200050004000100120002000
64004294715001100120002000100020002000300017251800050002000200050004000100120002000
64004294685001100120002000100020002000300017251800050002000200050004000100120002000
64004294715001100120002000100020002000300017251800050002000200050004000100120002000

Test 2: throughput

Count: 8

Code:

  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  st4 { v0.d, v1.d, v2.d, v3.d }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3202071601454001858012316004416001880123160046160038240369272045764018640020720016004816004820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202051601114001858012316004416001880123160046160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040012032009680023160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100
3202041600454001078010316000416000080103160006160002240309272006964002640011120016000816000820040002032001680003160000160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3200271601534000958003316004416001880033160046160002240039272002064002640002120160008160008204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204001203200968002316000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600464000118001116000016000080010160000160000240030272006364000040001020160000160000204000003200008000116000016000010
3200241600454000118001116000016000080010160000160038240099272100564018640011720160048160048204000003200008000116000016000010