Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STNP (D)

Test 1: uops

Code:

  stnp d0, d1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
900641362029110141014101410008743400020001000100020002000110001000
900424122001110001000100010008747400020001000100020002000110001000
900423162001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000
900423012001110001000100010008749400020001000100020002000110001000

Test 2: throughput

Count: 8

Code:

  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  stnp d0, d1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0379

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680149160155101800368001810080038800013001413742320026160107200800068000620016001216001218000080000100
16020583081160153101800348001810080036800013001413904320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016007216007218000080000100
16020483029160105101800048000010080006800013001413778320026160107200800068000620016001216001218000080000100
16020483029160105101800048000010080006800313001414083320146160167200800368003620016001216001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0378

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002680148160065118003680018108003880000301413667320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483033160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080031301414083320146160077208003680036201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010
16002483025160011118000080000108000080000301413703320000160010208000080000201600001600001800008000010