Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STNP (Q)

Test 1: uops

Code:

  stnp q0, q1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
900540672019120182000884320002000400012000
900423862001120002000920320002000400012000
900423092001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000
900423022001120002000919720002000400012000

Test 2: throughput

Count: 8

Code:

  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  stnp q0, q1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0753

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020516015016011910116001810016000130028267681601012001600082003200161160000100
16020416597816010110116000010016000130028268041601012001600082003200161160000100
16020516601116011810116001710016000130028268041601012001600082003200161160000100
16020416597816010110116000010016000130028268041601012001600082003200161160000100
16020416597816010110116000010016000130028268041601012001600082003200961160000100
16020416597816010110116000010016000030028283131601002001600082003200161160000100
16020416602816010110116000010016000130028277041601012001600082003200161160000100
16020416602816010110116000010016000130028277041601012001600082003200161160000100
16020516605916011810116001710016000130028277041601012001600082003200161160000100
16020416602816010110116000010016000130028277041601012001600082003200161160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0753

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600261601971600461101600351001600033028267621600132016001020320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600003028268011600102016000020320096116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600343028269321600442016004820320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010
1600241659781600111101600001001600003028268011600102016000020320000116000010